Wafer based beol process for chip embedding

ABSTRACT

In various embodiments a semiconductor device is provided, including a semiconductor body including a drift region and a gate electrode arranged adjacent to the drift region; and a contact structure provided over the drift region of the semiconductor body and having a first metal layer, an adhesion layer over the first metal layer and a second metal layer over the adhesion layer.

RELATED APPLICATION(S)

This application is continuation of U.S. patent application Ser. No.14/171,839, filed Feb. 4, 2014, entitled “WAFER BASED BEOL PROCESS FORCHIP EMBEDDING”, the contents of which are hereby incorporated byreference in their entirety.

TECHNICAL FIELD

Various embodiments relate to a wafer based BEOL (back end of line)process for chip embedding.

BACKGROUND

Packaging is the final stage of semiconductor device fabrication, inwhich the small block of processed semiconductor, i.e. the chip, isplaced in a supporting case that prevents physical damage and corrosion.The case, which is commonly referred to as “package”, supports theelectrical contacts which connect the chip to a circuit board.

A standard packaging process is usually based on bonding and molding.Interconnects are realized by a galvanic processes and the die isprotected with a laminate.

In a new packaging concept, also referred to as Blade package, a chip isattached onto a circuit board. Both the front side and the back side ofthe chip are electrically contacted with the leadframe via a metallayer. The Blade package is a vertical transistor package optimized forhigh current handling and easy circuit board layout. Using thistechnology makes it possible to realize products with lowest on stateresistances and highest power density without compromises in performanceand cooling.

However, it has been found that common chip concepts, for examplerelying on SFETx (x standing for 3, 4 or 5) technology, also referred toas “double poly” (i.e. designs with two electrodes insulated from oneanother in a trench) or its brand name Optimos, are not suitable for theBlade package due to the nature of the metallisation and/or passivationprocess and therefore, a solution to that problem would be desirable.

SUMMARY

In various embodiments a semiconductor device is provided, including asemiconductor body including a drift region and a gate electrodearranged adjacent to the drift region; and a contact structure providedover the drift region of the semiconductor body and having a first metallayer, an adhesion layer over the first metal layer and a second metallayer over the adhesion layer.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters generally refer to the sameparts throughout the different views. The drawings are not necessarilyto scale, emphasis instead generally being placed upon illustrating theprinciples of the invention. In the following description, variousembodiments of the invention are described with reference to thefollowing drawings, in which:

FIG. 1A shows a cross-sectional view of a vertical structure of a fieldeffect transistor manufactured in accordance with a standard process;

FIG. 1B shows a top view of the vertical field effect transistor shownin FIG. 1B;

FIG. 2 shows a vertical structure of a field effect transistor accordingto various embodiments;

FIG. 3 shows a semiconductor device according to various embodiments;

FIG. 4 shows a further semiconductor device according to variousembodiments; and

FIGS. 5 and 6 show methods for manufacturing a semiconductor deviceaccording to various embodiments.

DESCRIPTION

The following detailed description refers to the accompanying drawingsthat show, by way of illustration, specific details and embodiments inwhich the invention may be practiced.

The word “exemplary” is used herein to mean “serving as an example,instance, or illustration”. Any embodiment or design described herein as“exemplary” is not necessarily to be construed as preferred oradvantageous over other embodiments or designs.

The Blade package may be understood as an application of the printedcircuit board (PCB) in the semiconductor manufacturing technology. Inthe packaging process, a die may be attached to a leadframe bysoldering, such that the back side of the die may be electricallycontactable. The front side of the die may be also electricallycontacted by a metal layer.

FIG. 1 shows a vertical structure of a field effect transistor 100. Thevertical field effect transistor 100 may be manufactured in accordancewith the SFET5 technology standard which is a trench technology forpower transistors.

The transistor 100 includes a semiconductor body 102 which includes asemiconducting material 103, for example a layer of the semiconductormaterial 103, and a back side metal layer 104. The back side metal layer104 is provided on the bottom surface of the layer of semiconductormaterial 103 and may be used as a thermally optimized die attach bymeans of diffusion soldering or eutectic bonding. The semiconductormaterial 103 may be a part of a die incorporating a functional circuit.Differently doped wells may be created within the layer of semiconductormaterial 103 by means of doping. In this case, a gate electrode 106 isprovided in the layer of semiconductor material 103. A first driftregion 108 and a second drift region 110 are provided in the layer ofsemiconductor material 103 adjacent to the gate electrode 106. A layerof dielectric material isolating the gate electrode 106 from thesurrounding semiconductor material 103, e.g. from the drift regions 108,110, is not shown in FIG. 1A. The manufacture of the semiconductor body102 is performed during the so-called FEOL (front end of line) process.The explicit design of the semiconductor body 102 as schematically shownin FIG. 1A, e.g. the geometrical shape of the doped regions within thelayer of semiconductor material 103 is only an exemplary one and may beof course adapted to the specific circuitry which is to be manufactured.

Over the upper surface of the semiconductor body 102 a gate portion 112is provided which may be electrically coupled to the gate electrode 106.The gate portion 112 is covered by a layer of dielectric material 122, aso-called inter layer dielectric (ILD). The dielectric material mayinclude silicon oxide or silicon nitride. A first metal layer 118 isdisposed over the upper surface of the semiconductor body 102 on bothsides of the gate portion 112. The first metal layer 118 is subdividedin two or in general more portions thereof, for example a left portionand a right portion referring to the relative locations of therespective portions of the first metal layer 118 on the semiconductorbody 102, which are separated from one another by the gate portion 112and are further isolated from the gate portion 112 by the dielectricmaterial 122. A further gate portion 114 is provided on the uppersurface of the semiconductor body 102 adjacent to the left portion ofthe first metal layer 118 and isolated therefrom by the dielectricmaterial 122 which covers or surrounds the further gate portion 114 inthe same way as the gate portion 112 is surrounded by the dielectricmaterial 122. A further first metal layer 118* is provided on the uppersurface of the semiconductor body 102 adjacent to the right portion ofthe first metal layer 118. The further first metal layer 118* isseparated from the right portion of the first metal layer 118 by a blockof dielectric material 122.

A second metal layer 124, 124* is provided on top of every first metallayer 118, 118*. The second metal layer 124, 124* may include copper.The left portion of the second metal layer 124 over the left and rightportion of the first metal layer 118 is a continuous second metal layer124, i.e. the left portion and the right portion of the first metallayer 118 are electrically coupled to one another by means of the secondmetal layer 124. The other, right portion of the second metal layer 124*on top of the further first metal layer 118* is electrically isolatedfrom the continuous second metal layer 124 by means of a passivationmaterial 126 provided in a gap separating the left portion of the secondmetal layer 124 form the right portion of the second metal layer 124*.The passivation material is further provided over the leftmost layer ofdielectric material 122 and also on the right side of the right portionof the second metal layer 124*. Due to the nature of the manufacturingprocess of the field effect transistor 100 involving heating, anintermetallic phase 120, 120* is present at every interface between thefirst metal layer 118, 118* and the second metal layer 124, 124*.

The left portion and the right portion of the first metal layer 118 andthe further portion of the first metal layer 118* may be formed in thesame manufacturing process. In fact, a continuous first metal layer, forexample including aluminium, may be provided over the top surface of thesemiconductor body 102 and subsequently the continuous first metal layermay be structured appropriately (e.g. by an appropriate masking processfollowed by an etching process) to yield the pattern of first metalportions shown in FIG. 1A. The left portion and the right portion of thefirst metal layer 118 may be source contacts of the vertical fieldeffect transistor 100. The further portion of the first metal layer 118*may be a gate contact or gate pad of the vertical field effecttransistor 100. The gate contact is electrically coupled to the gateportion 112 and to the further gate portion 114. This, however, is notshown in FIG. 1A which is a cross-sectional view of the vertical fieldeffect transistor 100.

FIG. 1B shows a corresponding top view of the vertical field effecttransistor 100 from FIG. 1A. The top view shows the stage of themanufacturing process after the source contacts (i.e. the two portionsof first metal layers 118 having a rectangular shape in FIG. 1B), thegate contact 118*, the gate portion 112 and the further gate portion 114have been provided on the top surface of the semiconductor material 102.The gate portion 112 (not shown in FIG. 1A) may be a so-called gatefinger which provides an electrical connection between the main gatecontact 118* and the gate electrode 106 (not shown in FIG. 1B) buriedwithin the semiconductor material 103. The further gate portion 114 (notshown in FIG. 1B) may be a so-called gate runner which may be seen as aframe structure surrounding the source contacts and providing anelectrical connection between the gate contact 118* and the gate portion112. Furthermore, the further gate portion 114 may have a positiveeffect on the build-up of a homogenous electric field controlling theswitching of the device. It is to be noted that the dimensions of theelements shown in FIG. 1B, in particular their widths and lengths, maydiffer from their dimensions expected from FIG. 1A. FIG. 1B merelyserves a better schematical understanding of the vertical field effecttransistor 100 and should not be perceived as limiting in that sense.Furthermore, the design of the gate portion 112 in combination with thefurther gate portion 114 and the gate contact 118* is only one exampleof very many possible ways to implement that structure.

Returning back to the cross-sectional view presented in FIG. 1A, it maybe seen that the first drift region 108 and the second drift region 110are both provided underneath the source contacts, i.e. underneath theleft portion and right portion of the first metal layer 118. The whitearrows within the drift regions 108, 110 indicate the path of chargecarriers once an appropriate electric field has been applied to the gatecontact 118*. In analogy to the above description, the left portion ofthe second metal layer 124 and the right portion of the second metallayer 124*, which may include copper, may be formed in the same processstep, wherein a uniform second metal layer, for example includingcopper, may be provided over the semiconductor body 102 with the firstmetal layer 118, 118* and the dielectric layer 112 being alreadystructured. Subsequently, the uniform second metal layer may bestructured according to need to arrive at the pattern including the twoportions of the second metal layer 124, 124* as shown in FIG. 1A. Inparticular, the left portion of the second metal layer 124 arranged overthe left portion and the right portion of the first metal layer 118,i.e. the portion of the second metal layer 124 provided over the twosource contacts, is electrically isolated from the portion of the secondmetal layer 124* over the gate contact 118*. In addition, thepassivation material 126 is provided at least in the gap between theleft portion of the second metal layer 124 and the right portion of thesecond metal layer 124*.

In the scope of this specification, the reference numbers of layersfalling into the scope of the gate contact carry a suffix in the form ofasterisk (*), whereas corresponding layers falling into the scope of thesource contacts carry the same reference numbers without the asterisk.

The thickness of the layer including the semiconductor material 103 instandard manufacturing processes is approximately in the range ofapproximately 40 μm to approximately 60 μm. The layers provided on thesurface of the semiconductor body 102 add at least approximately further20 μm, such that the thickness of the whole structure of the verticalfield effect transistor 100 shown in FIG. 1A (the thickness beingmeasured from the bottom surface of the back side metal layer 104 to theupper surface of the passivation layer 126) may lie in the range ofapproximately 60 μm to approximately 70 μm or more.

The design of the vertical field effect transistor 100 shown in FIG. 1Amanufactured in accordance with the Optimos technology may be improvedin several aspects such that its migration into the Blade packagedescribed at the outset is less error-prone. In the following, severalissues inherent in the design shown in FIG. 1A will be discussed.

One undesirable aspect of the vertical transistor 100 design is theformation of the intermetallic phase 120, 120* at the interfaces betweenthe several portions of the first metal layer 118, 118* and the portionsof the second metal layer 124, 124*. The formation of the intermetallicphase 120, 120* is caused by high temperature process steps during themanufacture of the vertical field effect transistor 100. Theintermetallic phase 120, 120* is unwanted in the Blade assembly processand is seen as a flawed region since it is mechanically unstable andthus prone to cause delamination within the device. It is furthersusceptible to increased etching with respect to other materials suchthat is reduce the process reliability during the assembly of thedevice.

A second problematic aspect to be mentioned relates to the secondmetallic layer 124, 124*. Since structuring of copper layers is ratherdifficult, the standard thickness of the second metal layer 124, 124*leads to an insufficient thickness after roughening of the copper layer.During provision of vias through a uniform layer of the passivationmaterial 126 by means of a laser, for example, that thin layer maysuffer from melting open, down to materials located beneath, for exampledown to the intermetallic phase 120, 120* or even down to the level ofthe first metal layer 118, 118* which then becomes exposed, renderingthe electrical behaviour of the corresponding electrical contact less oroven predictable.

Furthermore, as shown in FIG. 1A, the left portion of the second metallayer 124 is a continuous layer or a plate which extends from a regionabove the left portion of the first metal layer 118 to the region abovethe right portion of the first metal layer 118, thereby covering andbeing in contact with the dielectric layer 122 which is disposed overthe gate portion 112. The continuous layer of second metal layer 124(i.e. the left portion of the second metal layer 124) helps inestablishing a uniform electrical potential thereon and on the twoportions of the first metal layer 118 corresponding to source contacts.The electrical contact between the continuous layer of the second metallayer 124 and the leadframe is mostly established by bonding orsoldering. However, the presence of the second metal layer 124 above thedielectric layer 122 as well as the interfacial contact between thosetwo layers is problematic. The second metal layer 124 material, thatusually being copper, has a relatively high coefficient of thermalexpansion in contrast to the relatively low coefficient of thermalexpansion of the underlying dielectric material 122. Hence, during thefrequent and common temperature changes in the manufacturing process,the second metal layer 124 may exert a shearing force upon thedielectric layer 122 located underneath. This may result in cracks inthe dielectric material 122, and, as a worst case scenario, may lead toleakage currents between the left portion of the second metal layer 124representing the source contact plate and the gate portion 112 being anintegral part of the gate structure.

Last but not least, the conventional passivation procedure may proveproblematic, as the openings in the passivation material 126 exposingthe second metal layer 124, 124*, as mentioned above, may lead to thealready too thin second metal layer 124, 124* (usually copper) to beexposed to the roughing procedure performed on the device during itsmanufacture.

In view of the above problems, the design of the vertical field effecttransistor 100 shown in FIG. 1A may be favourably changed as will beexplained based on the semiconductor device 200 shown in FIG. 2.

FIG. 2 shows a cross-sectional view of the semiconductor device 200according to various embodiments. The position of the cross-sectionwithin the device corresponds to that of FIG. 1A, as indicated in FIG.1B. As the semiconductor device 200 according to various embodimentswhich in this case is configured as a vertical field effect transistoris similar to the vertical field effect transistor 100, the samecomponents/elements will be labelled with the same reference numbers andthey will not be described again. Emphasis will be placed onspecifically altered aspects which may enable successful integration ofthe corresponding semiconductor chip into the Blade package.

The semiconductor device 200 includes the semiconductor body 103 havingthe semiconductor material 103 (e.g. a layer 103 of semiconductormaterial) and the back side metal layer 104 provided on the bottom sideof the semiconductor material 103. The doped structures within thesemiconductor material 103 may correspond to the ones described withrespect to FIG. 1A, i.e. at least one gate electrode 106 and at leastone drift region, e.g. two drift regions 108, 110 may be providedtherein by means of doping. A first metal layer 118 including a leftportion of the first metal layer 118 and a right portion of the firstmetal layer 118, each provided on either side of the gate portion 112and separated therefrom by the dielectric material 122 is also providedon the top surface of the semiconductor body 102, as already describedwith respect to FIG. 1A. Furthermore, the further gate portion 113covered by dielectric material 122 and a further portion of the firstmetal layer 118* are also provided.

The semiconductor device 200 according to various embodiments shown inFIG. 2, in contrast to the device structure shown in FIG. 1A has adifferent contact structure. Each of the contacts includes a stack oflayers and it may be seen that there is no interconnection between theindividual contacts at the level of the second metal layer 124, 124* aswas the case in the device of FIG. 1A. In detail, the semiconductordevice 200 includes a first contact structure 204, a second contactstructure 206 and a third contact structure 208. The first contactstructure 204 is arranged on the semiconductor body 102 over the firstdrift region 108. The second contact structure 206 is arranged on thesemiconductor body 102 over the second drift region 110 next to thefirst contact structure 204, spaced apart therefrom and electricallyisolated therefrom by a block of dielectric material 122 which coversthe gate portion 122 and by a portion of passivation material 126. Thethird contact structure 208 is arranged on the semiconductor body 102next to the second contact structure 124, spaced apart therefrom by thedielectric material 122 and a portion of passivation material 126.

The first contact structure 204 may correspond to a first sourcecontact, the second contact structure 206 may correspond to a secondsource contact and the third contact structure 208 may correspond to agate contact structure. The reference numbers of layers belonging to thegate contact structure are additionally marked with an asterisk, eventhough structurally they may be similar or substantially equal to theother contact structures. As the contact structures may be structurallysimilar, only the first contact structure 204 will be described indetail. Even though the contact structures may be substantially similar,they may differ in their dimensions or specific materials used such thatdifferent materials may be used for a given layer as long as theysatisfy certain requirements such as conductivity or availability ofetching agents, just to name two examples.

The first contact structure may include the first metal layer 118, anadhesion layer 202 arranged over the first metal layer 118 and a secondmetal layer 124 arranged over the adhesion layer 202. The first metal118 layer may include aluminium (Al) or an aluminium copper alloy,wherein the content of copper may amount to approximately 0.5%. Theandesion layer 202 may include titanium (Ti), tantalum (Ta), titaniumtungsten (TiW) or other refractive metals. The second metal layer 124may include copper (Cu).

As already mentioned, the contact structures 204, 206, 208 areelectrically separated from one another by a layer of dielectricmaterial 122 and portions of the passivation material 126 provided onthe layers of dielectric material 122. Furthermore, the passivationmaterial 126 may encapsulate the contact structures such that they arenot exposed to the exterior. However, openings in the passivationmaterial may be provided to expose the second metal layer 124, 124* forelectrical contacting, of which one opening 128 is shown in FIG. 2. Oncecorresponding openings have been provided over the further contactstructures, for example by means of a laser or by an etchant, a RDL(redistribution layer) may be used to interconnect the first contactstructure 204 with the second contact structure 206 and further toprovide electrical connections between the contact structures 204, 206,208 and the leadframe (not shown in FIG. 2) to which the semiconductordevice 200 according to various embodiments may be attached.

In the following, the differences between the field effect transistordesign presented in FIG. 1A and the one presented in FIG. 1B will bediscussed.

The adhesion layer 202, 202* provided between the first metal layer 118,118* and the second metal layer 124, 124* may offer several effects. Onthe one hand, the adhesion layer 202, 202* may improve the adhesionbetween the first metal layer 118, 118* and the second metal layer 124,124*. It has been observed that the mechanical stress within the Bladepackage is increased in comparison to other standard packages, forexample the Sx08 package. The Sx08 package may refer to a standard SMD(surface-mounted device) leadless mold package with a leadframe to whicha chip is soldered to. The Sx08 package may be further characterized bya wire bonded or clip soldered gate contact and an ordinary clipsoldered source interconnect. Despite providing an optimal boundarysurface between the first metal layer 118, 118* and the second metallayer 124, 124*, for example between Al and Cu, via the correspondingintermetallic phases with a thickness of approximately 700 nm,delamination still occurred in typical stress tests. By providing theadhesion layer 202, 202* including an Al and Cu separating material suchas Ti, Ta or TiW, a better adhesion between the surface of the firstmetal layer 118, 118* and the surface of the second metal layer 124,124* may be achieved and delamination at that interface may be avoided.On the other hand, the adhesion layer 202, 202* may increase the rangeof available manufacturing temperatures during manufacturing processessuch as providing the passivation layer, laser-drilling of vias formetallic interconnects. For example, depositing an imide basedpassivation is hardly possible without formation of intermetallic phasesif the adhesion layer 202, 202* is not in place. The temperaturerequired for imide passivation curing leads to a very strongintermetallic phase formation which, in effect, renders thecorresponding electrical contact inoperable. In that sense, the adhesionlayer 202, 202* may be seen as a layer preventing a reaction between thefirst metal layer 118, 118* and the second metal layer 124, 124*, forexample during the imide passivation curing and may therefore be areaction preventing and adhesion layer 202. Furthermore, the adhesionlayer 202, 202* may increase the process reliability, since it providesa solid stoppage layer during the process of providing openings 128 inthe passivation material 126 by a laser. In other words, the adhesionlayer 202, 202* may prevent a faulty drilling of the via hole (opening128) beyond the adhesion layer 202, 202*. With regard to this aspect,the non-existence of the intermetallic phase 120, 120* (see FIG. 1A) maybe also seen as beneficial, since the interface between the differentintermetallic phases is mechanically unstable. In case of anunintentional drilling through the second metal layer 124, 124* whilethe openings 128 in the passivation material 126 are provided, theintermetallic phase 120, 120* may be removed thereby exposing the firstmetal layer 118, 118* to succeeding wet processes in which the firstmetal layer 118, 118* may be removed or partially etched, such that thesurface of the semiconductor material 103 may be exposed. That chain ofevents may in effect render the contact electrically inferior.

The thickness of the second metal layer 124, 124* is increased withrespect to standard designs and may lie in the region of 5 μm or moreand may amount to 6 μm, 7 μm, 9 μm, 10 μm or more, for example. Theincreased thickness of the second metal layer 124, 124* allows for asecure roughening thereof which takes place at a later time during themanufacturing process. A thickness of the second metal layer 124, 124*below 5 μm may be critical in that respect as during the rougheningprocess it may be completely removed at some spots. The provision of athicker second metal layer 124, 124* may further increase the thermalcapacity and the stability with regard to electromigration. Thoseaspects become, determined by the system, particularly relevant at thecircumferential edge of the interface between the opening 128 (or via)and the second metal layer 124, 124*. During operation, a steady currentflow approximately 3.5 A may be carried by the via which may have adiameter of approximately 50 μm. However, the current density within thebulk of the material filling the via, e.g. copper, is practically zeroas the current predominantly flows at the edge of the block of materialfilling the via, e.g. The transition from the via to the second metallayer 124, 124* may be particularly critical at the circumferential edgeof the via in common designs having a thin layer of the second metallayer 124, 124* as the thin metal layer 124, 124* may need to handlevery high current densities. Here, the provision of a thicker secondmetal layer 124, 124* in accordance with various embodiments may bebeneficial. A thicker second metal layer 124, 124* translating into ahigher conductivity, may enable a wider field of design possibilitiesand may remove the necessity to electrically connect each source contactat a dense contact spacing by a via to achieve a homogenous currentdistribution. Furthermore, the provision of a thicker second metal layer124, 124* may increase the robustness of the corresponding field effecttransistor in avalanche mode. In case of copper as the materialcomprised by the second metal layer 124, 124*, common depositionprocedures such as PVD (physical vapour deposition) or ECD(electrochemical deposition) may be used.

As shown in FIG. 2, the second metal layer 124, 124* covers the firstmetal layer 118, 118* in each region of a contact structure or, in otherwords, it is deposited over the first metal layer 118, 118*, for examplealuminium, such that no portion of the first metal layer 118, 118*remains exposed which may improve processability. In comparison to thestandard design of a vertical field effect transistor 100 shown in FIG.1A, the provision of separate, discrete contact structures 204, 206, 208may be advantageous in the sense that there is no second metal layer124, 124* provided on the dielectric material 122 covering the gateportion 112. The gate portion 112 which may include (or be processedfrom) the first metal layer 118, 118* is not covered by the second metallayer 124, 124* but is only covered by the passivation material 126.This may prevent the formation of cracks in the dielectric material 122and leakage currents between the second metal layer 124 and the gateportion 112 as there is no drastic difference between the coefficient ofthermal expansion of the dielectric layer 122 and the coefficient ofthermal expansion of the passivation material 126.

The semiconductor device 200 according to various embodiments mayfurther include a tungsten layer (not shown in FIG. 2) arranged betweenthe first metal layer 118, 118* and the surface of the semiconductormaterial 103. During manufacture of the semiconductor device 200 thetungsten layer may undergo a fine pitch structuring process in order toprovide connections for connecting small current and/or temperaturesensors which may be sensing structures, for example, embedded in thedrift region provided within the semiconductor material 103. The currentsensor may be based on a reference cell which has a known surface area.By measuring the current flow though that reference cell, the currentflow though the contact structure may be derived. The temperature sensormay be, for example, based on a polysilicon resistor which has atemperature dependent resistance and may be placed within thesemiconductor device 200 according to various embodiments. The finepitch structured tungsten layer may provide fine connection structures(e.g. wires) for connecting the sensors with corresponding controllers.

The layer of passivation material 126 may include various organicmaterials such as imide or epoxy. After the passivation material 126 hasbeen deposited on the semiconductor device 200 according to variousembodiments, the openings 128 may be provided in the passivationmaterial 126 for contacting the second metal layer 124, 124*, forexample by a laser. However, the passivation layer 126 may remainunperforated or “unopened” (i.e. without openings 128 being providedtherein) and the openings 128 may be provided therein, for example bydrilling with a laser, when the wafer is being diced by means of a sawframe. This allows more flexibility with respect to the used packagetechnology (such as die attach, roughening of the second metal layer)and may lead to a more stable mechanical connection between the chip andthe package.

A further difference between the standard vertical field effecttransistor 100 shown in FIG. 1A and the semiconductor device 200according to various embodiments may be seen in the usage of a thinwafer technology. As mentioned previously, the whole workpiece as shownin FIG. 1A may have a thickness in the range of approximately 60 μm toapproximately 100 μm. The thickness of the layer of the semiconductormaterial 103 may lie in the range of approximately 40 μm toapproximately 80 μm such that a thickness of the whole semiconductordevice 200 according to various embodiments, measured from the bottomsurface of the back metal layer 103 to the upper surface of the layerincluding the passivation material 126, may lie in the range ofapproximately 70 μm or less. This allows for a more efficientmanufacturing of the wiring structure, for example the RDL, forelectrical contacting of the contact structures 204, 206, 208 and of theback side metal layer which may be configured as a drain contact of thedevice. The openings 128 (or vias) in the passivation material 126 tothe source contact structures 204, 206 and the openings (or vias) in thesurrounding passivation material 126 to the drain contact may have thesame geometrical shapes. Due to the relatively small thickness of thelayer containing the semiconductor material 103, they may besimultaneously filled galvanically with the metallic material formingthe wiring structure. By employing thin substrates leading to thin chipswith a thickness of 70 μm or less, the overall topography may be heldvery compact. Due to the relatively small offset between the surface ofthe leadframe (not shown in FIG. 2A) on which the semiconductor device200 may be mounted and the surface of the semiconductor device 200(corresponding to the upper surface of the layer containing thepassivation material 126) of approximately 70 μm or less, the laminatingprocess of the semiconductor device 200 to the leadframe may beperformed without a pre-structured laminate material without stabilizingfillers which would be necessary if the described offset was larger.

The electrical and thermal coupling of the semiconductor device 200according to various embodiments to the leadframe may be achieved by athin metallic soldering connection. The soldering connection as such maybe performed by means of diffusion soldering or eutectic soldering. Thematerials used for that process may include metal compounds on the basisof gold (Au), tin (Sn) and/or copper (Cu).

The aspects described above are based on structural features which havebeen also explained on the basis of FIG. 2. Each structural feature mayhave a number of favourable effects on a corresponding semiconductordevice. It goes without saying that not all aspects need to be realizedin a semiconductor device. The described aspects may rather be seen as acatalogue of individual features having certain advantages ifimplemented, and the person skilled in the art may implement anarbitrary combination of those to solve problems he or she is facedwith. However, it may well be that implementing a larger number of thedescribed features into a semiconductor device may have a synergeticeffect. The described aspects may prove helpful in modifying standardmanufacturing processes to produce semiconductor devices which may besuccessfully used with the Blade packaging technology. In the following,reference numbers already used while discussing the vertical fieldeffect transistor 100 shown in FIG. 1A and the semiconductor device 200according to various embodiments shown in FIG. 2 will be used.

In FIG. 3, a semiconductor device 300 according to various embodimentsis shown. The semiconductor device 300 may include a semiconductor body102 having a drift region 108 and a gate electrode 106 arranged adjacentto the drift region 108; and a contact structure 204 provided over thedrift region 108 of the semiconductor body 102 and having a first metallayer 118, an adhesion layer 202 over the first metal layer 118 and asecond metal layer 124 over the adhesion layer 202. The semiconductordevice 300 according to various embodiments may be further complementedby any number of beneficial features described above with reference tothe semiconductor device 200 shown in FIG. 2A.

FIG. 4 shows a semiconductor device 400 according to various furtherembodiments. The semiconductor device 400 may include a semiconductorbody 102 having a first drift region 108, a second drift region 110 anda gate electrode 106 arranged between the drift regions. Thesemiconductor device 400 according to various embodiments may furtherhave a first contact structure 204 provided over the first drift region108 of the semiconductor body 102 and having a first metal layer 118 anda second metal layer 124 over the first metal layer 118; a secondcontact structure 206 provided over the second drift region 110 of thesemiconductor body 102 and having a first metal layer 118 and a secondmetal layer 124 over the first metal layer 118, wherein the secondcontact structure 206 is laterally separated from the first contactstructure 204. The semiconductor device 400 according to variousembodiments may be further complemented by any number of beneficialfeatures described above with reference to the semiconductor device 200shown in FIG. 2A.

FIG. 5 shows a flow diagram 500 which outlines a method formanufacturing a semiconductor device, for example the semiconductordevice 400 shown in FIG. 4. In a first step 502, the method may includeproviding a semiconductor body including a drift region and a gateelectrode arranged adjacent to the drift region. In a next step 504, themethod may include depositing a first metal layer over the drift regionof the semiconductor body. In a next step 506, the method may includedepositing an adhesion layer over the first metal layer. In a next step508 the method may include depositing a second metal layer over theadhesion layer, wherein the stack comprising the first metal layer, theadhesion layer and the second metal layer forms a contact structure.Further process steps may be added in accordance with the physicalfeatures of the semiconductor device 200 according to variousembodiments described above.

FIG. 6 shows a flow diagram 600 which outlines a further method formanufacturing a semiconductor device, for example the semiconductordevice 300 shown in FIG. 3. In a first step 602, the method may includeproviding a semiconductor body including a first drift region, a seconddrift region and a gate electrode arranged between the drift regions. Ina next step 604, the method may include depositing a first metal layerover the semiconductor body. In a further step 606, the method mayinclude depositing a second metal layer over the first metal layer. In ayet further step 608, the method may include removing a portion of thefirst metal layer and a portion of the second metal layer in a regionbetween the first drift region and the second drift region therebyforming a first contact structure over the first drift region and asecond contact structure over the second drift region, wherein the firstcontact structure and the second contact structure are laterallyseparate from one another and each comprise a portion of the secondmetal layer arranged over a portion of the first metal layer Furtherprocess steps may be added in accordance with the physical features ofthe semiconductor device 200 according to various embodiments describedabove.

In accordance with various embodiments, a semiconductor device isprovided which may include a semiconductor body including a drift regionand a gate electrode arranged adjacent to the drift region; and acontact structure provided over the drift region of the semiconductorbody and having a first metal layer, an adhesion layer over the firstmetal layer and a second metal layer over the adhesion layer.

According to various further embodiments, the semiconductor device mayfurther include a further drift region arranged adjacent to the gateelectrode such that the gate electrode may be arranged between the twodrift regions.

According to various further embodiments the semiconductor device mayfurther include a further contact structure provided over the furtherdrift region of the semiconductor body and having a first metal layer,an adhesion layer over the first metal layer and a second metal layerover the adhesion layer.

According to various further embodiments of the semiconductor device thesecond contact structure may be laterally separated from the firstcontact structure.

According to various further embodiments of the semiconductor device thefirst metal layer of the contact structure and the first metal layer ofthe further contact structure may include aluminium.

According to various further embodiments of the semiconductor device theadhesion layer of the contact structure and the adhesion layer of thefurther contact structure may include titanium tungsten.

According to various further embodiments of the semiconductor device thesecond metal layer of the contact structure and the second metal layerof the further contact structure may include copper.

According to various further embodiments of the semiconductor device thesecond metal layer may have a thickness of more than 5 micrometers.

According to various further embodiments the semiconductor device mayfurther include a gate portion provided over the gate electrode of thesemiconductor body between the contact structures_and electricallycoupled to the gate electrode.

According to various further embodiments the semiconductor device mayfurther include a dielectric material provided between the contactstructures and covering the gate portion.

According to various further embodiments the semiconductor device mayfurther include passivation material provided over the dielectricmaterial between the contact structures. The passivation material may bealso provided over portions of the contact structures.

According to various further embodiments of the semiconductor device theupper surfaces of the second metal layer of the contact structure and ofthe second metal layer of the further contact structure may be level.

According to various further embodiments of the semiconductor device thepassivation material may be provided over the contact structures therebyencapsulating the contact structures.

According to various further embodiments the semiconductor device mayfurther include an opening provided in the passivation material over theupper surface of each of the contact structures exposing the uppersurface of each of the contact structures.

According to various further embodiments the semiconductor device mayfurther include a further gate portion provided over the semiconductorbody and electrically coupled to the gate portion, the further gateportion being covered by a dielectric material.

According to various further embodiments the semiconductor device mayfurther include a gate contact structure provided over semiconductorbody and having a first metal layer, an adhesion layer over the firstmetal layer and a second metal layer over the adhesion layer, whereinthe first metal layer of the gate contact structure may be electricallycoupled with the gate portion and the further gate portion.

According to various further embodiments the semiconductor device mayfurther include a tungsten layer arranged between the first metal layerof each of the contact structures and the semiconductor body.

According to various further embodiments of the semiconductor device thetungsten layer may include interconnections to connect a sensor formeasuring at least one of temperature and current. The tungsten layermay be a fine pitch structured tungsten layer.

According to various further embodiments, the adhesion layer may be areaction protection and adhesion layer.

In accordance with various further embodiments, a semiconductor deviceis provided which may include a semiconductor body including a firstdrift region, a second drift region and a gate electrode arrangedbetween the drift regions; a first contact structure provided over thefirst drift region of the semiconductor body and having a first metallayer and a second metal layer over the first metal layer; a secondcontact structure provided over the second drift region of thesemiconductor body and having a first metal layer and a second metallayer over the first metal layer, wherein the second contact structuremay be laterally separated from the first contact structure.

According to various further embodiments the semiconductor device mayfurther include an adhesion layer provided between the first metal layerand the second metal layer within each of the contact structures.

According to various further embodiments of the semiconductor device thefirst metal layer of the first contact structure and the first metallayer of the second contact structure may include aluminium.

According to various further embodiments of the semiconductor device theadhesion layer of the first contact structure and the adhesion layer ofthe second contact structure may include titanium tungsten.

According to various further embodiments of the semiconductor device thesecond metal layer of the first contact structure and the second metallayer of the second contact structure may include copper.

According to various further embodiments of the semiconductor device thesecond metal layer may have a thickness of more than 5 micrometers.

According to various further embodiments the semiconductor device mayfurther include a gate portion provided over the gate electrode of thesemiconductor body between the contact structures and electricallycoupled to the gate electrode.

According to various further embodiments the semiconductor device mayfurther include dielectric material provided between the contactstructures and covering the gate portion.

According to various further embodiments the semiconductor device mayfurther include passivation material provided over the dielectricmaterial between the contact structures. The passivation material may bealso provided over portions of the contact structures.

According to various further embodiments of the semiconductor device theupper surfaces of the second metal layer of the first contact structureand of the second metal layer of the second contact structure may belevel.

According to various further embodiments of the semiconductor device thepassivation material may be provided over the contact structures therebyencapsulating the contact structures.

According to various further embodiments the semiconductor device mayfurther include an opening provided in the passivation material over theupper surface of each of the contact structures exposing the uppersurface of each of the contact structures.

According to various further embodiments the semiconductor device mayfurther include a further gate portion provided over the semiconductorbody and electrically coupled to the gate portion, the further gateportion being covered by a dielectric material.

According to various further embodiments the semiconductor device mayfurther include a further contact structure provided over semiconductorbody and having a first metal layer, an adhesion layer over the firstmetal layer and a second metal layer over the adhesion layer, whereinthe first metal layer of the further contact structure may beelectrically coupled with the gate portion and the further gate portion.

According to various further embodiments the semiconductor device mayfurther include a tungsten layer arranged between the first metal layerof each of the contact structures and the semiconductor body.

According to various further embodiments of the semiconductor device thetungsten layer may include interconnections to connect a sensor formeasuring at least one of temperature and current. The tungsten layermay be a fine pitch structured tungsten layer.

According to various further embodiments the semiconductor device mayfurther include a backside metal layer provided on the backside of thesemiconductor body.

According to various further embodiments of the semiconductor device thesemiconductor device may be configured as a vertical transistor.

According to various further embodiments of the semiconductor device thebackside metal layer may be configured as a drain terminal.

According to various further embodiments of the semiconductor device thefirst contact structure and the second contact structure may beconfigured as source terminals.

In accordance with various embodiments a method for manufacturing asemiconductor device is provided, wherein the method may includeproviding a semiconductor body including a drift region and a gateelectrode arranged adjacent to the drift region; depositing a firstmetal layer over the drift region of the semiconductor body; depositingan adhesion layer over the first metal layer; and depositing a secondmetal layer over the adhesion layer, wherein the stack comprising thefirst metal layer, the adhesion layer and the second metal layer mayform a contact structure.

In accordance with various further embodiments a method formanufacturing a semiconductor device is provided, wherein the method mayinclude providing a semiconductor body including a first drift region, asecond drift region and a gate electrode arranged between the driftregions; depositing a first metal layer over the semiconductor body;depositing a second metal layer over the first metal layer; removing aportion of the first metal layer and a portion of the second metal layerin a region between the first drift region and the second drift region,such that a first contact structure is formed over the first driftregion and a second contact structure is formed over the second driftregion, wherein the first contact structure and the second contactstructure are laterally separate from one another and each include aportion of the second metal layer arranged over a portion of the firstmetal layer.

While the invention has been particularly shown and described withreference to specific embodiments, it should be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the spirit and scope of the invention asdefined by the appended claims. The scope of the invention is thusindicated by the appended claims and all changes which come within themeaning and range of equivalency of the claims are therefore intended tobe embraced.

To the extent any amendments, characterizations, or other assertionspreviously made (in this or in any related patent applications orpatents, including any parent (U.S. patent application Ser. No.14/171,839), sibling, or child with respect to any art, prior orotherwise, could be construed as a disclaimer of any subject mattersupported by the present disclosure of this application, Applicanthereby rescinds and retracts such disclaimer. In particular, Applicantrescinds any disclaimer in the parent application, U.S. patentapplication Ser. No. 14/171,839, that may have resulted from theamendment to the claims of the parent application that lead to theallowance of the claims therein. Applicant respectfully submits that anyprior art previously considered in the parent application or any otherrelated patent applications or patents, including any parent, sibling,or child, may need to be re-visited or reconsidered.

What is claimed is:
 1. A semiconductor device, comprising: asemiconductor body having a front side and a back side opposite to thefront side, the semiconductor body comprising a semiconductor layer, afirst drift region and a first gate electrode arranged laterallyadjacent to the first drift region, wherein the first gate electrodevertically extends from the front side of the semiconductor body towardsthe back side of the semiconductor body, and a first contact structureprovided over the semiconductor body and at least partially horizontallyoverlapping the first drift region of the semiconductor body, the firstcontact structure including a first metal layer contacting thesemiconductor body at the front side, an adhesion layer disposed overthe first metal layer, and a second metal layer disposed over theadhesion layer, wherein the first metal layer of the first contactstructure and the first gate electrode do not horizontally overlap. 2.The semiconductor device of claim 1, further comprising: a secondcontact structure provided over the semiconductor body and laterallyadjacent to the first gate electrode, the second contact structureincluding a first metal layer contacting the semiconductor body at thefront side, an adhesion layer disposed over the first metal layer, and asecond metal layer disposed over the adhesion layer, wherein the firstmetal layer of the second contact structure and the first gate electrodedo not horizontally overlap.
 3. The semiconductor device of claim 2,further comprising: a second drift region of the semiconductor body,wherein the first gate electrode is arranged laterally adjacent to thesecond drift region; and wherein the second contact structure at leastpartially horizontally overlaps the second drift region of thesemiconductor body.
 4. The semiconductor device of claim 2, furthercomprising: a gate portion disposed at the front side of thesemiconductor body, wherein the gate portion is electrically coupled tothe first gate electrode and is at least partially disposed between thefirst and second contact structures.
 5. The semiconductor device ofclaim 2, further comprising: a third contact structure provided over thesemiconductor body, the third contact structure including a first metallayer contacting the semiconductor body at the front side, an adhesionlayer disposed over the first metal layer, and a second metal layerdisposed over the adhesion layer, wherein the first metal layer of thethird contact structure is physically and electrically coupled to gateportion.
 6. The semiconductor device of claim 5, wherein top surfaces ofthe first metal layers of the first, second, and third contactstructures are coplanar.
 7. The semiconductor device of claim 2, whereinthe first metal layers of the first and second contact structuresinclude aluminum.
 8. The semiconductor device of claim 2, wherein theadhesion layers of the first and second contact structures includetitanium, tantalum, or titanium tungsten.
 9. The semiconductor device ofclaim 2, wherein the second metal layers of the first and second contactstructures include copper.
 10. The semiconductor device of claim 4,further comprising: dielectric material provided between the first andsecond contact structures that covers the gate portion.
 11. Thesemiconductor device of claim 10, further comprising: passivationmaterial provided over the dielectric material between the first andsecond contact structures.
 12. The semiconductor device of claim 11,wherein the passivation material is further provided over the first andsecond contact structures so as to encapsulate the contact structures.13. The semiconductor device of claim 12, further comprising: an openingprovided in the passivation material over the upper surface of each ofthe first contact structure exposing an upper surface of the firstcontact structure.
 14. The semiconductor device of claim 4, furthercomprising: a further gate portion provided over the semiconductor bodythat is electrically coupled to the gate portion, the further gateportion being covered by dielectric material.
 15. The semiconductordevice of claim 2, wherein the second contact structure is laterally andphysically separate from the first contact structure.
 16. Thesemiconductor device of claim 2, wherein upper surfaces of the secondmetal layer of the first contact structure and of the second metal layerof the second contact structure are level.
 17. The semiconductor deviceof claim 4, wherein upper surfaces of the first metal layer of the firstcontact structure and of the gate portion are level.
 18. Thesemiconductor device of claim 1, further comprising: a back side metallayer provided at the back side of the semiconductor body.
 19. Thesemiconductor device of claim 2, wherein a thickness of the second metallayer of the first and second contact structures is the range from 5 μmto 10 μm.
 20. The semiconductor device of claim 1, wherein a thicknessof the semiconductor device is in the range from 60 μm to 100 μm.